Power and delay analysis of CMOS multipliers using Vedic algorithm

This paper presents an effective Vedic algorithm called as Urdhva-Tiryyagbhyam Sutra implementation and design for multipliers using 45nm technology. Multiplier is one of the most important parts of almost all digital system hardware, so a high speed, reduced delay, reduced area and low power consumption multiplier design will results in effective digital system designs. Thus this paper present an effective design and implementation of a multiplier with high speed, reduced delays, less area and low power consumption using our ancient methodology of Vedic mathematics that is Urdhva-Tiryagbhyam Sutra. This implementation is done in 45nm technology using chip designing tool Cadence Virtuoso at backend. Implemented Multiplier consumes very low power because of its carry skip addition methodology, reduced hardware and reduced delays. A 2 Bit multiplier consumes a very low power 5.5489×10
^-11
watt and delay of 1.924×10
^-12
sec and 4 Bit multiplier consumes power of 0.0002854 watt and delay of 2.0873×10
^-7
sec.