StatCC: A statistical cache contention model

Chip multiprocessor (CMP) architectures sharing on chip resources, such as last-level caches, have recently become a mainstream computing platform. The performance of such systems can vary greatly depending on how co-scheduled applications compete for these shared resources. This work presents StatCC, a simple and efficient model for estimating the contention for shared cache resources between co-scheduled applications on chip multiprocessor architectures. StatCC leverages the StatStack cache model to estimate the co-scheduled applications' cache miss ratios, and a simple performance model that estimates their CPIs based on the estimated miss ratios. These methods are combined into a system of equations that models the contention for the shared cache resources and can be solved to determine the CPIs and miss ratios of the co-scheduled applications. The result is a fast algorithm with a 2% error across SPEC CPU2006 benchmark suite compared to a simulated CMP system with a hierarchy of private and shared caches. Furthermore, the profiling data used by StatCC is collected with a runtime overhead of only 40%.