Implementation of efficient portable low delay adder using FPGA

No doubt that in this technological era the arithmetic circuit is the core of most all the Digital Signal Processing applications (DSP), especially adder circuits. In this paper, various types of adder circuits have been implemented on Field Programmable Gate Array (FPGA). Furthermore, another architecture for adder called Carry Shifting Adder (CSHA) is proposed. This depends on shifting the carry to the next stage. Then it's combined with a carry increment circuit to get a low delay. The goal of this paper is to efficiently carry out the proposed CSHA adder with carry increment circuit over FPGA kit. Simulations are done to find out the circuit area and delay. Also, this is compared with the related other adder circuits. The performance of this proposed adder circuit is better than other related ones in both area and delay.