Design and Evaluation of an Efficient Schmitt Trigger-Based Hardened Latch in CNTFET Technology

This paper presents a Schmitt trigger (ST) buffer using carbon nanotube FET (CNTFET) for reliable low-power applications. Nanoscale circuits are more susceptible to transient faults or soft errors due to the reduction of the stored charge in their sensitive nodes. Hereupon, low-cost and tolerant circuits design is a significant challenge, especially in the nanoscale storage cells. In addition, the proposed ST is utilized for designing a low-power hardened latch. In the proposed design, instead of up-sizing and increasing the input capacitance, the determined hysteresis mechanism of the proposed ST buffer is utilized to improve the single event upset hardness. The simulations are conducted based on the Stanford CNTFET model at 16-nm technology node. According to the results, the proposed ST has on average 90% lower power-delay product and higher robustness to PVT variations as compared to its most efficient CNTFET-based counterparts. Moreover, the simulations confirm the considerable tolerance of the proposed hardened latch to the multiple node upset as compared to the state-of-the-art designs. The proposed hardened latch has on average 68% higher critical charge, which considerably enhances its reliability and on average 16% smaller area as compared to its counterparts.