An 8-bit 1.25GS/s CMOS IF-sampling ADC with background calibration for dynamic distortion

An 8-bit, 1.25-GS/s subsampling ADC with digital background calibration for frequency-dependent distortion is presented in this paper. The derivative-based dynamic distortion model is extended to linearize the ADC frontend including the input buffer and the T/H. A low sampling rate auxiliary ADC is included on chip to acquire real-time, high-linearity reference samples to enable continuous background calibration. The digital post-distortion (applied off chip) enables SFDR improvements of 10 dB for 2.5 GHz inputs. Temperature sweeps from 10°C to 80°C confirm the scheme's robustness.