Development of a Parallel-FET Linearization Technique for High Efficiency GaN Power Amplifiers

We demonstrate the design of a linear and high efficient power amplifier (PA) by using different gate bias voltages for parallelly combined Gallium Nitride (GaN) high electron mobility transistors (HEMTs). The experimental results show that the linearized PA achieves the gain flatness of 0.3 dB over a 35 dB power range and has a measured sharp output power at 1 dB compression point (P1dB) of 38.5 dBm, less than 2 dB below the saturated power (PSAT). The measured adjacent channel power ratio (ACPR) of the proposed linearized PA shows up to 8 dB improvements over the PA biased ~ class A (47% I_dss).