High Performance Tri-Gate GaN Power MOSHEMTs on Silicon Substrate

We demonstrate high-performance GaN power metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on silicon substrate based on a nanowire tri-gate architecture. The common issue of partial removal of carriers by nanowire etching in GaN tri-gate transistors was resolved mainly by optimized tri-gate geometry, including filling factor and trench width. The tri-gate reduced the OFF-state leakage current (I
_OFF
) and the subthreshold slope, increased the ON/OFF ratio, and improved the breakdown voltage (V
_BR
) of the device. With a gate-to-drain separation (L
_GD
) of 5 μm, the tri-gate MOSHEMTs exhibited V
_BR
of 792 V at I
_OFF
of 0.3 μA/mm, along with a small specific ON-resistance (R
_{ON, SP}
) of 0.91 ± 0.08 mΩ·cm
²
. With LGD of 15 μm, hard V
_BR
of 1755 V at I
_OFF
of 45 μA/mm with high soft V
_BR
of 1370 V at I
_OFF
= 1 μA/mm were achieved, rendering excellent high-power figure of merits (FOMs) up to 1.25 GW/cm
²
. These results unveil the significant potential of nanostructured GaN transistors for future power applications.