An 802.11a/b/g/n Digital Fractional- $N$ PLL With Automatic TDC Linearity Calibration for Spur Cancellation

A fractional-N digital phase-locked loop (PLL) architecture with low fractional spur is presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to achieve wide detection range with fine resolution. The TDC is calibrated automatically utilizing the ramp signal generated from the fractional-N accumulator for optimal linearity. A digi-phase spur cancellation technique with automatic TDC gain tracking is also implemented to further suppress the fractional spurs. The chip also includes an improved multimodulus divider (MMD) structure that overcomes the glitch problem during division ratio toggling associated with the prior art MMDs, enabling carrier synthesis across wide frequency range continuously. As part of an 802.11a/b/g/n transceiver, the DPLL can provide coverage for both 2.4/5 G WiFi bands. The proposed fractional-N DPLL is implemented in a 55-nm CMOS technology. The DPLL achieves a largest fractional spur level of -55 dBc without using a sigma-delta modulator and an in-band phase noise of -107 dBc/Hz (0.55 ps integrated jitter) while consuming 9.9 mW.