Integrated circuit fault prognostics based on the delay characteristics of the clock network

This study proposes an integrated circuit fault prediction technique, which is based on delay characteristics of the clock network. A typical digital integrated single road was used as the example to study the responses of the clock network delay signals to the integrated circuit failures, and analyzed the feasibility and effectiveness of the method in detail. The experimental results show that the fault diagnosis rate of the method was as high as 92%; after spectrum analysis, the delay signals were converted to the amplitudes and phases, the relation between the phases and the degradation rates was a single exponential function, and the phases of the device was increased, the degradation rate was reduced, with decreasing the sweep frequency. The phases of the range of the degradation rates is from 50% to 80%, can be defined the fault diagnosis threshold or warning interval of the device. At lower frequency, the gradient of the phase was more slowly, so the error of prognostics is smaller at low frequency, the accuracy of prognostics is higher.