Elimination of metal bridging failure in VLSI metallization and yield enhancement of FLAT ROM device

A few lots of wafers (FLAT ROM) were reported with low yield (5-20%) issue. RIE, SEM and EDX techniques were used to identify the root causes. Al metal filaments were found at particular locations, which had resulted in metal bridging failure. They were found to be due to the narrow space between the two polysilicon layers and insufficient metal etching. The solution to eliminate these metal filaments is to increase overetch of L90 from 100 to 135 or change the space between the two poly layers. After using a new overetch recipe [135], the wafer sort yield was greatly enhanced.