Design, analysis and performance comparison of GNRFET based adiabatic 8-bit ALU

The advancement of transistor process technology reduces the chip area at the cost of power consumption. Adiabatic logic is one of the promising low power techniques, which gives low power dissipation at the cost of delay. The proposed work optimizes delay using MOS-GNRFET as the device instead of Si-MOSFET and proposes ECRL logic based 8bit ALU architecture performing 4 arithmetic and 4 logical operations. The Kogge-stone parallel adder structure is used in the ALU to reduce delay owing to the pipelined architecture of ECRL and lower number of stages in kogge-stone adder. ALUs in CMOS, ECRL and GNRFET-ECRL have been designed for 10nm process technology and are simulated using Hspice. The CMOS, ECRL and GNRFET-ECRL ALUs are having power dissipation values of 38.75mW, 14.131 DW and 158.799nW respectively.