Fast one- and two-pick fixed-priority selection and muxing circuits

Priority encoders and arbiters usually drive multiplexers (muxes). Latency optimization of priority encoders and multiplexer trees has usually been handled separately in the literature. However, in some applications with circular data dependencies, the combined latency of the arbiter and muxing needs to be optimized. Moreover, there is an ever growing need for throughput. This requires switches that pick and multiplex more than one request per cycle. In this paper, we propose a family of circuit topologies where priority encoding picks one or two requests and takes place in parallel with muxing. We first present a scalable logic circuit for the 1-pick fixed-priority muxing problem and then extend it to the 2-pick problem. We compare the proposed architecture to its counterpart that does only priority encoding using Synopsis Design Compiler with ARM-Artisan TSMC 180 nm worst-case standard library. The results show that most of the priority encoding latency is hidden in the proposed circuit topology.