A CMOS RMS-to-DC converter using /spl Delta//spl Sigma/ multiplier-divider

A novel topology for CMOS /spl Delta//spl Sigma/ RMS-to-DC converters is described. Analysis shows that the proposed topology is insensitive to most circuit imperfections except offset voltages. A test circuit of a 1st-order single-ended RMS-to-DC converter is realized in a 0.8 /spl mu/m double-poly CMOS process. Experimental results demonstrate that input waveforms with crest factors as high as 3 can be measured at the 800 mV full-scale input level. It provides a maximum relative error of /spl plusmn/1% of reading.