Design and performance comparison of adiabatic 8-bit multipliers

The advancement of transistor process technology reduces chip area at the cost of the total power consumption. Adiabatic logic, one of the promising low power techniques in VLSI gives low power dissipation at the expense of delay. In any digital hardware, the fundamental building blocks contribute to significant power dissipation and propagation delay. Multipliers are one among them which are of prime importance in Digital Signal Processing (DSP) and Image Processing applications. The present work proposes ECRL based 8-bit multiplier designs and compares them with the CMOS designs. Wallace-Dadda hybrid multiplier which uses Decomposition Logic to reduce the carry propagation delay is considered to be the reference design. 8-bit Vedic-Dadda hybrid multiplier and 8-bit Vedic multiplier are presented as power optimized designs. Hspice is used to obtain the power and delay values of the designed multipliers in CMOS and ECRL. 8-bit Vedic multiplier provides a power reduction of about 19.3% as compared to Wallace-Dadda hybrid multiplier. Overall, the proposed ECRL based multiplier dissipates about 77% less power, as compared to CMOS designs.