SiO2/4H-SiC interface traps effects on the input capacitance of DMOSFET

In this paper, an analytical model is presented to describe the input capacitance of Power-MOSFETs in 4H polytype of Silicon Carbide (4H-SiC). In order to provide an instrument for accurate interpretations of C-V measurements and for a deeper understanding of the device operations, the model describes the charge variations induced by the presence of the oxide-semiconductor interface trapped charge. Their energy dependence has been accounted to describe the charge dynamics into the channel and the accumulation layer and proved by comparisons with numerical simulations.