Optimization of IC-Stripline Performance by Response Surface Space-Mapping Technique

This paper presents the design optimization of the closed version of the IC-Stripline. The geometrical parameters of the IC-Stripline are optimized in order to improve the voltage standing wave ratio (VSWR). Time-consuming direct optimization by three-dimensional electromagnetic (3-D EM) simulations is avoided by implementation of the response surface space-mapping technique. The implemented technique sequentially builds up the response surface model according to the results obtained from the new iterations of the 3-D EM simulation. Based on 3-D EM simulation results the parameters of the equivalent circuit model are extracted. The extracted parameter values form the response surface that is modeled by the radial basis functions. The search for the optimal design point is performed by the design space exploration (Voronoi tessellation algorithm) and the problem exploitation (gradient method optimization of the response surface models). The presented technique results in efficient optimization performed in a small number of iterations. The IC-Stripline is manufactured according to the presented optimization results and VSWR less than 1.25 in the frequency range up to 4.4 GHz is obtained.