A physical parametric transistor model for CMOS circuit simulation

A transistor model for use in simulation of analog and digital CMOS circuits is described. This model treats inversion devices and normally off accumulation devices individually. The analysis, based on surface potential, is carried out in voltage space. Single expressions for drain current and terminal charges are obtained that conserve charge and give accurate DC, AC, and transient solutions. Derivatives of current and charges are continuous, thus removing a major source of nonconvergence in circuit simulation. The model precalculates and stores charge densities, requiring significantly less computer memory than table look up methods while still describing devices with arbitrary channel width-to-length ratios. The need for measuring device capacitance is eliminated because terminal charge and capacitance are computed from the same parameters that are used to compute drain current. Because the parameters are physical, the model can be used to monitor and predict the effect of process changes. The model has been implemented in the SPICE circuit simulation program and a variety of typical devices and circuits have been simulated successfully. CPU time requirements are comparable to the existing SPICE model.<
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