Cost-effective co-verification using RTL-accurate C models

The verification quality of a system on chip (SOC) design depends on the number of simulations that can be performed under time-to-market constraints. This in turn depends on both the simulation speed and the cost of multiple simulator licenses. Since HDL simulators are both slow and expensive, design quality suffers. This paper presents a methodology and associated tools for the use of RTL-accurate C models for fast and cost-effective verification.