A constraint-based placement refinement method for CMOS analog cell layout

The performance of analog circuits is sensitive to fabrication process and the layout of their physical masks. In this paper, a novel constraint-based methodology is proposed for the placement refinement of CMOS analog cell circuits. Constraint-based module generation and shaping process are also developed not only to optimize the layout shape, area but more importantly to guarantee the analog circuits performance. A hybrid-tree model is proposed to simultaneously represent the geometry, symmetry and parasitic constraints for the layout. Experimental results have shown the effectiveness of the proposed method.