Dynamic analysis in discrete time delta domain for unstable bicycle system

This work is inspired from a challenging project conducted with undergraduate students within Automatic Control and Computer Engineering Faculty of Iasi. A bicycle type system was implemented and analyzed. In order to control this type of system, fast sampling rate is required. The finite precision nature of the existing digital hardware involves the choice of computational operations restricted to a finite number of bits. Even more so, the control algorithms must be implemented on control units with limited word length in the context of fast sampling. On the other hand, the mathematical design approach gives infinite-precision ideal values. The implementation stage is a critical step since the representation in finite precision must be performed as close to the ideal one. The discrete time delta (δ) domain representation is proposed due to its accuracy loss minimization at high sampling frequency comparing to discrete time shift (q) representation counterpart. The advantage of using δ operator is more pronounced as the number of bits used for finite word length implementation is lower. In this paper, a dynamic analysis of a real bicycle system is performed and discrete time δ domain representation is proposed, considering low bit number representation. Hence, δ domain representation allows implementation of different algorithms on cheaper processors without loss of performances.