A data cache optimization approach for coarse grain reconfigurable architecture for multimedia applications

This paper proposes a data Cache optimization method for coarse grain reconfigurable architecture for multimedia applications to improve the data flow of the reconfigurable system with low on-chip memory cost, including the novel data Cache structure and the related Cache management strategy, especially the updating method for the data Cache. The proposed data cache structure has been adopted in a reconfigurable system called REMUS-HPP. The experimental results show that the approach is efficient for various multimedia applications, and the memory access performance of the reconfigurable system can be improved by 47.02%-53.20% with a very low memory cost of 4Kbytes.