A 0.048ns/°C delay generator with variation self-calibration structure(VSCS) for HVICs

A fully on-chip delay generator with a PVT variation self-calibration structure (VSCS) is proposed in this paper. To eliminating the delay variation and ensuring the signal integrity, a proportional to absolute temperature (PTAT) current and a proportional to supply voltage (PTSV) current is adopted in the VSCS. In addition, a bias circuit consisting of positive and negative temperature coefficient resistors is developed to obtain the temperature compensated delay. HVIC adopting the proposed delay generator is implemented in a 0.5 μm 600V Bipolar-CMOS-DMOS (BCD) process. Measured results show that the average temperature coefficient of the proposed delay generator is 0.048ns/°C.