An Op-amp free SAR-VCO hybrid ADC with second-order noise shaping

This paper presents a novel SAR-VCO hybrid 1-1 MASH ADC, where a passive 1
^st
-order noise-shaping SAR ADC eliminates Op-amp in the first stage. A VCO-based ADC digitizes the residue of SAR ADC with one additional noise-shaping order in the second stage. The inter-stage gain error is suppressed by a foreground calibration. A prototype ADC is designed in a 65nm CMOS process. The transistor-level simulation results show that 75.7 dB SNDR and 14.9 fj/conversion-step FoM are achieved in the 5 MHz bandwidth at 60 MS/s under 1.0 V supply.