An improved structure to enhance the robustness of SiC power MOSFETs for a low Ron, sp

An improved structure of Silicon Carbide (SiC) power MOSFET with a central implanted region (CIR) introduced to the middle of JFET area to alleviate the high gate oxide field is presented in this paper. Combined with a higher doped current spreading layer (CSL), the CSL+CIR structure can further reduce the specific on-resistance (R
on
, sp) of the device without the need of a tightened JFET width to protect the gate oxide from the high drain bias. According to the technology computer aided design (TCAD) simulations, the superior performance can be maintained at a wide range of JFET width, resulting in a good compromise between performance development and reduced processing tolerance. Additionally, no extra processing steps are required, which makes the CSL+CIR structure another choice for mass production of SiC power MOSFETs.