A 0.68-to-1.44 GHz low-jitter all-digital phase-locked loop with a novel PFD and a high resolution DCO in 0.μm CMOS

A low-jitter and wide output frequency range ADPLL was proposed in this paper. The adopted PDF based on sense-amplifier flip-flop (SAFF) can effectively improve the jitter performance. The novel DCO with cascading structure consists of a coarse-tuning delay chain and a fine-tuning interpolator, obtaining both wide frequency tuning range and high resolution. A high-resolution TDC was employed in this design. The TDC can adaptively scale its resolution according to the input phase error difference, using an integer TDC and a sub-exponent TDC. The proposed ADPLL was designed in SMIC 0.18μm CMOS process. The output frequency of the ADPLL ranges from 0.64 to 1.44 GHz with a 40MHz reference frequency. When the output frequency is 1.28GHz, the peak-to-peak and rms jitters are 22.3ps and 2.1ps respectively. The maximum power consumption is 24.43mW at (1.8v, 1.44GHz). With respect to the recently proposed high-performance ADPLLs, the proposed ADPLL shows advantages in smaller area, lower jitter and wider output frequency range.