Design Kernel Exploration Using QBF-Based Boolean Matching

The synthesis and mapping of user designs to configurable hardware is typically performed by heuristics. These approaches analyze the decomposability of the combinational user functions as a starting point and derive appropriate mappings to LUT structures or pull them in from pre-computed implementation libraries. In everyday use, this generally achieves a very competitive trade-off between the time spent for the synthesis and the quality of the produced implementations. A higher pressure on the optimality of an implementation exists when implementation libraries are generated or when critical kernels that are extensively duplicated in a massively parallel design are implemented. In these cases, a formal statement that an implementation within fewer LUTs or a smaller combinational depth is strictly impossible is very valuable. We present a tool that formulates the task of mapping a user design to a configurable hardware structure as a quantified boolean formula (QBF). It then uses a QBF solver to either compute an implementing configuration or to know for sure that the desired functionality cannot be implemented within the provided hardware. In the context of this tool, we also describe different approaches to model configurable interconnects and present the impact of these modelling approaches on the time needed to solve the mapping tasks.