A design of the new FPGA with data path logic and run time block reconfiguration method

This paper describes a design of the new FPGA, which has good performance in functional capacity and speed, and analyzes its performance. The functional density and speed performance are improved by inserting DPL (Data Path Logic), which is a special block having an extendable 4 bit adder/subtracter and multiplier, and by reconfiguring the switching points and configuration points using the RTBR (run time block reconfiguration) method, which has a reconfiguration memory for reusing the logic resource. This paper proposes CFB (configurable function block) and RTBR DPL as basic blocks of the new FPGA and explains the chip implementation of prototype of architecture.