A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications

A high-speed dual-modulus prescaler has been developed in 0.36 /spl mu/m CMOS. The prescaler was designed for low-power frequency synthesizers for 900 MHz to 1.9 GHz wireless applications. It provides programmable division ratio of 64, 65, 128, and 129. Power consumption was 2.9 mW with 1.9 GHz input frequency and 3.3 V power supply. The measured residual phase noises were -142 dBc/Hz at 100 Hz offset and -166 dBc/Hz at 100 kHz offset.