A bandpass sigma-delta modulator IC with digital branch-mismatch correction

A bandpass sigma delta modulator, integrated in a 0.35 /spl mu/m CMOS technology, samples a 82 MHz signal with a 109 MHz clock. The resolution is 11 bits over a 200 kHz bandwidth. To reach higher sampling rates the integrated circuit sub-samples the signal and uses the conventional two-branch parallel structure. A novel digital correction technique reduces the mismatch between the parallel branches increasing the signal to image ratio by 10 to 15 dB. This technique can be extended to structures with higher levels of parallelism.