High-reliability SpaceWire engine implemented on the SOISOC3 microprocessor: Components, short paper

SOISOC3 is our new space-grade system-on-chip processor which is currently being developed by MHI in partnership with JAXA. The chip is implemented on a 200 nm radiation hardened process based on the commercial SOI (Silicon On Insulator), so that can apply to the Space missions. This is the next generation system-on-chip processor upgraded from the currentSOISOC2 chip already used for ASTRO-H, ERG satellites, etc. SOISOC3 has a high-reliability SpaceWire engine, which MHI has developed, supporting for incoming SpaceWire standards for deterministic data delivery (SpaceWire-D), reliable data transfer service (SpaceWire-R), as well as high performance Remote Memory Access Protocol (RMAP) with Direct Memory Access (DMA) engine through a SpaceWire router. The SpaceWire engine is capable of acting as an RMAP initiator, target, or as a general purpose packet transmitter and receiver. Our developed SpaceWire-D and SpaceWire-R engine is mainly performed on hardware, and can achieve high accuracy scheduling and high performance, with less CPU load. We'll introduce the outline and current status of our development with an prototype evaluation board exhibited at MHI booth.