Low voltage low power 4/5 dual modulus prescaler in 180nm technology

In this paper, the design of dual-modulus divide-by-4/5 prescaler through sleepy keeper approach for NAND and NOR implementation and pseudo-NMOS based IETSPC-DFF topologies are used and simulated in 0.18μm CMOS process technology. As a result, the average power consumption of the prescaler is 0.236 mW and 0.248 mW and the propagation delay is 0.46ns and 0.49ns for divide-by-4 and divide-by-5 operation respectively. The pre-layout simulation outcomes shows that the prescaler has a maximum of 18 GHz operating frequency. The new approach of our divide-by-4/5 dual modulus prescaler has been compared with other recent implementation showing that the proposed circuit successfully tradeoff between various parameters like speed, power and frequency.