Fabrication process of copper lead frame chip scale package (LF-CSP)

In this study, a new packaging technique employing the copper LF-CSP was developed for memory devices. The technique is expected to be lower in production cost and better electrical performance compared with conventional packaging technique. In this paper, the simulation results on the electrical and thermal performance of the package, assembly process, selection of the UBM materials, and reliability of the LF-CSP are presented. In addition, the cost estimation of the LF-CSP was made in comparison with the conventional packaging technologies.