Dual-Gate Charge Trap Flash Memory for Highly Reliable Triple Level Cell Using Capacitive Coupling Effects

In this letter, the triple level cell (TLC) NAND flash memory with excellent properties was implemented by a thin film charge trap flash memory with a dual-gate structure by using the capacitive coupling effect between the front gate and back gate. As compared with the single-gate (SG) mode operation, a large memory window at low program and erase (P/E) voltages was obtained from the dual-gate (DG) mode operation owing to the capacitive coupled self-amplifying effect. The TLC was implemented by using the DG-mode operation with highly stable eight levels: a large threshold voltage difference >9 V per level was obtained under low operating voltages at <14 V with a fast P/E speed of
$100~\mu \text{s}$
. In contrast, the conventional SG mode was unfavorable to TLC. Furthermore, the DG mode showed a much smaller charge loss than the SG mode, resulting in stable retention and endurance characteristics at room temperature and high temperature.