An integrated manufacturing approach to chip packaging

This paper examines the considerations of an integrated manufacturing approach to substrate finishing and chip packaging. By performing critical substrate related processes such as plating, pin attach and test, the carriers are in a sense being prepared for assembly at the assembly house. Such close synergy between substrate processing and assembly translates into a real life understanding of carrier product specifications as it pertains to assembly sensitivity. In this paper, key characteristics of such an integrated approach are presented. Cost of manufacturability and quality aspects are discussed. Specifications for ceramic and plastic substrates are compared for both flip chip (C4) and wirebond assembly applications. Some examples of optimization case studies used to determine specification values are reviewed. Functional testing methods and capabilities for flip chip (C4) and wire bond products are described. Where applicable, aspects of substrate-assembly interactions within such optimisations and functional testing are addressed with respect to problem solving, analytical/engineering support and quality feedback.