A VLSI parallel architecture of a piecewise linear neural network for nonlinear channel equalization

This paper proposes a systolic architecture based on a multilayer neural network (MNN) to solve the problem of the nonlinear channel equalization. This architecture is based on a piecewise linear multilayer neural network (PL-MNN) algorithm derived from a recursive version (PL-RNN). In place of a sigmoid function, both algorithms use a canonical piecewise linear function, which makes the MNN more suitable for a digital VLSI implementation. The PL-MNN algorithm is more suitable for a VLSI pipelined implementation. The pipeline technique is applied to obtain a high throughput circuit which can be used in a high speed adaptive channel equalization. A performance study on both linear and nonlinear channels is presented. A comparison of results obtained with two conventional methods (LMS and RLS) and the PL-RNN algorithm is presented, and a performance evaluation of the systolic architecture is carried out for a 0.5 /spl mu/m CMOS technology.