FPGA implementation of secondary synchronization channel detector for WCDMA systems

This paper focuses on FPGA implementation of secondary synchronization channel detector for WCDMA systems, which is important task in identifying the code group number and slot id in WCDMA cell searching. Secondary synchronization codes in WCDMA cell are transmitted in parallel with primary synchronization process. Hierarchical cyclic codes are used. The work presented in this paper deals with a reconfigurable FPGA design using Verilog hardware description language to provide for realization of the frame synchronization and code group identification to be complied with 3GPP standard. The architecture proposed uses reduced number of matched filter taps so that it relatively reduces hardware complexity.