Design and Simulation of Low-Power Logic Gates Based on Nanoscale Side-Contacted FED

A new nanoscale device has been already introduced as a side-contacted field effect diode (S-FED), which is composed of a diode and planar SOI-MOSFET. In this paper, S-FED is optimized in terms of work function, with due attention to the design of logic gates, such as NOT, NAND, NOR, and XOR. Results demonstrate that optimum work function is 4.7 eV in which the highest value of ION/IOFF can be achieved. Mixed-mode simulations are used to determine the performance of the proposed logic gates. Also, the proof regarding the mitigation of the total power consumption up to 56% is presented so that not gate based on S-FED improves power delay product by about 30%, compared with the CMOS-based version. A similar fabrication process with the CMOS technology could be asserted as the considerable advantage to pave the way of feasibly realizing the new generation of S-FED-based logic gates.