A New Figure of Merit, ${\Delta V_{\text {DIBLSS}} /(I_{\rm {d},{\mathrm{ sat}}} /I_{\rm {sd},{\mathrm{ leak}}} )}$ , to Characterize Short-Channel Performance of a Bulk-Si n-Channel FinFET Device

This paper aims to investigate the device parameters, including drain-induced barrier lowering (DIBL), subthreshold swing (SS), and saturation drive current,
$I_{\rm d,{\mathrm{ sat}}} $
, of bulk-Si n-channel FinFET devices (bulk n-FinFETs). The impact of lightly doped drain (LDD) process on the performance of bulk n-FinFETs is also examined in this paper. According to our measured data, excluding LDD in bulk n-FinFETs not only reduces mask costs but it also enables slightly better short-channel control compared to the inclusion of LDD. A new figure of merit,
$\Delta V_{\mathrm{ DIBLSS}} /(I_{\rm d,{\mathrm{ sat}}} /I_{\rm sd,{\mathrm{ leak}}} )$
, is introduced for monitoring short-channel performance of bulk n-FinFETs, where
$\Delta V_{\mathrm{ DIBLSS}} $
accounts for the DIBL and SS, and
$I_{\rm sd,{\mathrm{ leak}}} $
is the source/drain subthreshold off-state leakage current.