Front-end readout system for PHENIX RICH

A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, source synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with 128-bits data bus. The total transaction time is estimated to be less than 30 /spl mu/s per event when this system is applied to the experiment. This result indicates that the performance is satisfied with the requirements of the PHENIX experiment.