20% n-Type silicon solar cell fabricated by a simple process with an aluminum alloy rear junction and extended emitter

A simple process is defined and executed to achieve 20% efficiency for cells fabricated on 156 mm n-Cz Si wafers. The cell structure is n
⁺
np
⁺
with the p
⁺
emitter being formed over most of the rear surface by Al alloying, but extended to the wafer edges by a light doping with B. The n
⁺
FSF is doped with P which makes the front surface easy to passivate and contact. B and P dopants are introduced into the wafer by ion implantation and are co-annealed in a single high temperature step, during which a passivating thermal oxide is also grown on the front and back surfaces. The back surface remains textured, and the entire process is additive as the cell structure is built layer-by-layer, with no subtractive steps needed for planarization, stripping diffusion glasses, or creating vias in dielectrics. A key benefit of the extended emitter is to improve p-n junction quality (since the depletion region is essentially confined within the interior of the silicon and does not intersect the surface), as indicated by the pseudo FF regularly exceeding 0.83. In addition, J
_sc
increases because of the reclaimed Si border area (Al to wafer edge). Cell parameters were found to be tightly distributed. The highest efficiency measured was 20.04% for a 239 cm
²
cell with a selective FSF and five busbars. Interconnecting cells in a module could be done with 3M Cu tape or Schmid Tin Pad applied directly to backside Al.