Modified quasi static energy recovery adiabatic logic implementation for low power application

This paper presents implementation of flip flops and 3 bit binary up counter using Modified Quasi State Energy Recovery Logic (MQSERL). Two phase power clock supply and its 180
⁰
phase shifted signal is used in MQSERL to minimize switching activities of circuit node. Initially circuits such as INVERTER, NAND, NOR, XOR and 2:1 multiplexer have been designed using MQSERL style and conventional CMOS logic. Comparative analysis has been done by computing power dissipation, propagation delay and Power Delay Product to validate the functionality of proposed MQSERL. Further D flip flop with preset and clear terminal have been designed using three input NAND gate and then 3 bit binary up counter using both the logic styles. All the circuits are simulated using 180nm tanner technology and at operating voltage of 1.8v. Clock frequency for MQSERL is set at 100MHz and input signal at 50 MHz. The MQSERL D flip Flop is 82.21% and 3 bit binary Counter is 94.40% power efficient over conventional CMOS logic.