Sub-lithographic Patterning via Tilted Ion Implantation for Scaling Beyond the 7-nm Technology Node

Tilted ion implantation (TII) can be used in conjunction with pre-existing masking features on the surface of a substrate to form features with smaller dimensions and smaller pitch. In this paper, the resolution limit of this sub-lithographic patterning approach is examined via experiments as well as Monte Carlo process simulations. TII is shown to be capable of defining features with size below 10 nm, in a self-aligned manner, reproducing with high fidelity the line-edge roughness of the pre-existing masking features. Since it has relatively low associated process cost, TII-enhanced patterning is a promising approach to advance high-volume manufacture of integrated circuits beyond the 7-nm technology node.