Modified 4-2 compressor using improved multiplexer for low power applications

This paper reports a modified 4-2 compressor by improving the multiplexer design from traditional transmission gates with the optimized pass transistors. The proposed design shows power consumption of 16.93 μW as compared to 24.99 μW for the traditional design. Further power delay product (PDP) of proposed design is 7.855 fJ as compared to 9.071 fJ for the traditional design. Moreover effect of substrate bias has been studied for proposed and traditional design. Proposed design shows the power consumption of 10.75 μW as compared to 16.32 μW for traditional design with reverse substrate bias voltage (Vsb) of −0.9V. Proposed design shows improvement in PDP of 4.837 fJ as compared to 5.206 fJ for traditional design. Effect of temperature variation has been studied on proposed and traditional design. The proposed and traditional designs have been simulated in 0.18μm technology using SPICE. The proposed design can be used in multipliers for various low power applications. Results show a significant enhancement in power delay product (PDP), transistors count and signal swing in the proposed design.