An Analytical Model of MOS Admittance for Border Trap Density Extraction in High- $k$ Dielectrics of III–V MOS Devices

In this paper, we have developed a straightforward MOS admittance-based technique for defect density extraction, utilizing analytical equations for MOS capacitors with border traps (BTs). We show that these equations can provide an efficient technique to obtain the BT density directly from the measured data without any requirement of numerically involved techniques. This is demonstrated by applying the methodology on measured C-V data from Al
₂
O
₃
- and HfO
₂
-based MOSCAPs. The extracted densities show less than 5% difference from the values extracted using the fitting-based methodology used in previous reports. We show that, due to the analytical nature of these equations, they can be used to understand the impact of each defect parameter on the admittance. We extensively prove the applicability of the analytical solution for a very wide range of parameter values. In addition, we lay out a methodology for defect density extraction, which can be easily automated for the characterization of large scale data sets of high-k dielectrics on III-V MOS devices.