A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture

The Instruction Set Architecture (ISA) determines the effect that a soft error on an instruction can have on the processor. Previous works have shown that the ISA has some intrinsic capability of detecting errors. For example, errors that change a valid instruction into an invalid instruction encoding or into an instruction that causes an exception. The percentage of detectable errors varies widely for each bit in the ISA. For example, errors on bits that are used for immediate or register values are unlikely to be detected while those that are used for the opcode are more likely to lead to an exception. In this paper, this is exploited by introducing a simple encoding of the instructions that does not require additional bits. The idea is that the decoding propagates the error so that it affects the most sensitive bit of the ISA and therefore it is more likely to be detected. As no additional bits are required, no changes or overheads are needed in the memory. The proposed scheme is useful when the memory is not protected with parity or Error Correction Codes. The only cost of implementing the technique are simple encoder and decoder circuits that are similar to a parity computation. This technique is applicable to any ISA, no matter the length of the opcodes or their location in the instruction encoding. The effectiveness of the proposed scheme has been evaluated on the ARM Cortex M0 ISA resulting in an increase in the error detection capability of up to 1.64x.