Analytic boundaries for 6T-SRAM design in standby mode

In this paper an analytic model is presented, whose purpose is to determine boundaries inside which supply voltage is minimized and leakage current is limited under manufacturing process variations for 6T-SRAM cells operating in standby mode. Drain-induced barrier lowering (DIBL) effects are considered in view of the fact that their influences become more critical in nanometer (below 90 nm) CMOS nodes, when devices are dimensioned with minimum sizes and operate in sub-threshold region. The analytic expressions were verified by comparisons with electrical simulation results obtained with a 28 nm FDSOI CMOS process.