Lateral field enhanced band-trap-band tunneling current in a 0.5 /spl mu/m "off" state mosfet

An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5 /spl mu/m LATID n-MOSFET. In the experiment, the device was subject to a DC voltage stress to generate interface traps. Based on our proposed band trap-band tunneling, the increased drain leakage current can be adequately described by an analytical expression of /spl Delta/I/sub d/=Aexp(-B/sub it//F) with a Bit of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.