A timing model for static CMOS gates

A simple but accurate delay model is presented for both simple and complex static logic gates. Unlike the previous delay models which assume the worst-case scenario, the present model has the capability of handling the different input switching conditions. In the delay analysis of a circuit, failing to take into account the position of the transistor that is switching can result in a delay value which is off by a margin of 100% or more from the actual. This novel modeling technique has been implemented in LISP on a TI Explorer II workstation Lisp Machine as a part of the DROID design automation environment.<
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