A design technique for high Q-factor SI filters

A problem of SI realisation of a high quality (Q) factor biquadratic filter is considered with emphasis on the signal-dependent clock feedthrough (SDCF) influence upon sensitivities of filter design parameters. The CMOS digital gate array-based implementation of medium Q-factor biquadratic filter resulted in a high random deviation of Q-factor value. An explanation of the phenomenon considered has been found by means of biquadratic filter model analysis taking into account the SDCF effect. It has been shown that a significant reduction of Q-factor sensitivities is possible to achieve through the use of an optimised DC-transfer-function voltage-to-current converter (VCC). A new S/sup 2/I memory cell utilising this VCC has been proposed and its advantage compared to the current state-of-the-art S/sup 2/I memory cell demonstrated.