Parallel performance directed technology mapping for FPGA

An efficient distributed method is developed for the technology mapping of look up table-based field programmable gate arrays. Parallelization shortens the design cycle time for rapid prototyping of large designs onto FPGA. In our algorithm, the Boolean network is partitioned using an effective k-way partitioning tool, the subgraphs are synthesized for performance using the nominal delay predict model, and then merged back to form the covering of the circuit. Blocks are processed independently in parallel on a network of workstations. Experimental results for a set of large combinational circuits from the LGSYNTH'91 benchmark suite show linear speedups. Produced designs are equivalent or better in terms of performance and area as compared to designs processed without partitioning.